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| CXK77V1810GB/TM-9/10/12 65,536-Word-by-18-Bit High-Speed CMOS Synchronous Static RAM Preliminary Description The CXK77V1810GB/TM is a high-speed CMOS synchronous static RAM with common I/O pins, organized as 65,536-words-by-18-bits. This synchronous SRAM integrates input registers, high-speed SRAM and output registers onto a single monolithic IC. All input signals, except OE, are latched at the positive edge of an external clock (CLK). The RAM data from the previous cycle is presented at the positive edge of the subsequent clock cycle. Write operation is initiated by the positive edge of CLK and is internally self-timed. This feature eliminates complex off-chip write pulse generation and provides increased flexibility for incoming signals. Asynchronous OE adds the flexibility of data bus control. 100MHz operation is obtained from a single 3.3V power supply. Functional Block Diagram CLK CE WE A0 A15 Features * High speed, low power consumption * Single +3.3V power supply: 3.3V 5% * Inputs and outputs are LVTTL/LVCMOS-compatible * Byte Select capability * Asynchronous OE * Common data input and output * 9ns cycle time (110MHz) * All inputs (except OE) and outputs are registered on a single clock edge * Self-timed write cycle * Package line-up: -- GB: 7 x 17 Plastic Ball Grid Array with 50mil pitch -- TM: 400mil, 50-pin TSOP II with .8mm pitch Register CLK Register Decoder CLK Self-Timed Write Logic 64Kx 18 RAM OE Sense Amp CLK Register I/O 0 I/O 17 Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. -1- Register Rev. 7.1 CXK77V1810GB/TM Pin Configuration (top view) CXK77V1810GB 1 A B C D E F G H J K L M N P R T U VDDQ NC NC DQ8 NC VDDQ NC DQ5 VDDQ NC DQ3 VDDQ DQ1 NC NC NC VDDQ 2 A0 NC A1 NC DQ7 NC DQ6 NC VDD DQ4 NC DQ2 NC DQ0 A15 A14 NC 3 A2 NC A3 VSS VSS VSS LB VSS NC VSS NC VSS VSS VSS NC A13 NC 4 NC NC VDD NC CE OE NC NC VDD CLK NC WE A12 A11 VDD NC NC 5 A4 NC A6 VSS VSS VSS NC VSS NC VSS UB VSS VSS VSS NC A10 NC 6 A5 NC A7 DQ9 NC DQ11 NC DQ13 VDD NC DQ15 NC DQ16 NC A8 A9 NC 7 VDDQ NC NC NC DQ10 VDDQ DQ12 NC VDDQ DQ14 NC VDDQ NC DQ17 NC NC VDDQ A4 A3 A2 A1 A0 CE DQ8 DQ7 VDDQ VSSQ DQ6 DQ5 VDD DQ4 DQ3 VSSQ VDDQ DQ2 DQ1 DQ0 WE A15 A14 A13 A12 CXK77V1810TM 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 A5 A6 A7 OE UB LB DQ9 DQ10 VDDQ VSSQ DQ11 DQ12 CLK VSS DQ13 DQ14 VDDQ VSSQ DQ15 DQ16 DQ17 A8 A9 A10 A11 Pin Description Symbol A0 to A15 DQ0 to DQ8 DQ9 to DQ17 VDD VDDQ VSSQ VSS Description Address input Lower Byte Data input/output Upper Byte Data input/output +3.3V power supply +3.3 output power supply Output ground Ground Symbol CLK LB UB CE WE OE Description Clock input Lower Byte enable input Upper Byte enable input Chip Enable input Write Enable input Output Enable input Separate VSSQ are available only in CXK77V1810TM. For proper operation, VDD VDDQ at all times, including power up. Absolute Maximum Ratings Item Supply voltage Input voltage Output voltage Allowable power dissipation Operating temperature Storage temperature Soldering temperature * time Symbol VDD VIN VO PD Topr Tstg Tsolder Rating -0.5 to +4.6 (Ta = +25C, GND = 0V) Unit V V V W C C C * sec -0.5 to VCC + 0.5 (4.6V max.) -0.5 to VCC + 0.5 (4.6V max.) 1.0 0 to +70 -55 to +150 260 * 10 -2- CXK77V1810GB/TM Truth Table CE (tn) H L L L L L L L L WE (tn) X H H H H H L L L UB (tn) X X H L H L L H L LB (tn) X X H L L H L L H OE X H X L L L X X X Read bits 0-17 Read bits 0-8 Read bits 9-17 Write bits 0-17 Write bits 0-8 Write bits 9-17 Don't care Don't care Don't care DIN(tn) DIN(tn) DIN(tn) DOUT(tn) DOUT(tn) DOUT(tn) Hi-Z Hi-Z Hi-Z ICC ICC ICC ICC ICC ICC Mode Deselect Read, output Hi-Z DQ0-17 (tn) Don't care Don't care DQ0-17 (tn+1) Hi Z Hi - Z VDD Current ISB ICC DC Recommended Operating Conditions Item Supply voltage Output supply voltage Input high voltage Input low voltage Symbol VDD VDDQ* VIH VIL Min. 3.15 3.15 2.0 -0.3** Typ. 3.3 3.3 -- -- (Ta = +25C, GND = 0V) Max. 3.45 3.45 VDD + 0.3** 0.8 Unit V V V V *VDDQ must be VDD at all times, including power up. **VIL = -1.5V min. and VIH = VDD +1.5V for pulse width less than 5ns. Electrical Characteristics DC and Operating Characteristics Item Input leakage current Output leakage current Operating power supply current Standby current Symbol ILI ILO IDD VIN = GND to VDD VO = GND to VCC OE = VIH Cycle = min. Duty = 100% IOUT = 0mA CE VIH Cycle = min. Duty = 100% IOUT = 0mA IOH = -2.0mA IOL = 2.0mA (VCC = 3.3V 10%, GND = 0V, Ta = 0 to = +70C) Test Conditions Min. -1 -1 -- Typ* -- -- -- Max. 1 1 220 Unit A A mA ISB -- -- 150 mA Output high voltage Output low voltage *VCC = 3.3V, Ta = +25C VOH VOL 2.4 -- -- -- -- 0.4 V V I/O Capacitance Item Input capacitance Output capacitance Symbol CIN COUT Test Conditions VIN = 0V VOUT = 0V Min. -- -- (Ta = +25C, f = 1MHz) Max. 5 7 Unit pF pF Note: These parameters are sampled and are not 100% tested. -3- CXK77V1810GB/TM AC Electrical Characteristics -9 Item Clock period Clock pulse high Clock pulse low Setup time Hold time Clock to output Clock to output high impedance Clock to output low impedance OE to output OE to output high impedance OE to output low impedance 1. All parameters are specified over the range 0 to +70C. 2. These parameters are sampled and are not 100% tested. Symbol tCP tCH tCL tS tH tCQ tHZ*2 tHZ*2 tOE tOHZ*2 tOLZ*2 Min. 9 3.5 3.5 2.0 0.5 2 -- 2 1 -- 1 Max. -- -- -- -- -- 5.5 5.5 -- 5 4.5 -- -10 Min. Max. 10 4 4 2.5 0.5 2 -- 2 1 -- 1 -- -- -- -- -- 6 6 -- 5 5 -- -12 Min. Max. 12.5 4 4 2.5 0.5 2 -- 2 1 -- 1 -- -- -- -- -- 7 6 -- 6 5 -- Unit ns ns ns ns ns ns ns ns ns ns ns AC Characteristics AC Test Conditions Item Input pulse high level Input pulse low level Input rise time Input fall time Input reference level Output reference level Output load conditions (VDD = 3.3V 5%, Ta = 0 to +70C) Conditions VIH = 2.4V VIL = 0.4V tr = 2ns tf = 2ns 1.4V 1.4V Figure 1 *1. Including scope and jig capacitance. *2. For tLZ, tHZ 30pF*1 868 5pF*1 868 I/O 1178 I/O 1178 Output Load (1) 3.3V Output Load*2 (2) 3.3V Figure 1 -4- CXK77V1810GB/TM Timing Waveform of Read Cycle CLK tCP tS A0-A15 n tH n+1 n+2 tCH tCL WE tS tH tS CE/UB/LB tH OE (VIL) tCQ DQ0-DQ17 Qn-2 Qn-1 tLZ Qn Timing Waveform of Write Cycle CLK tS A0-A15 n tH n+1 n+2 CE/UB/LB WE OE DQ0-DQ17 Dn Dn+1 Dn+2 -5- CXK77V1810GB/TM Timing Waveform of Read-Write-Read Cycle I (CE/UB/LB Control) CLK A0-A15 N N+1 N+2 N+3 N+4 CE/UB/LB WE tS tH OE (VIL) tCQ tHZ tS tH DN+2 tCQ DQ0-DQ17 QN-1 QN+3 Timing Waveform of Read-Write-Read Cycle II (OE Control) CLK A0-A15 N N+1 N+2 N+3 N+4 CE/UB/LB (VIL) WE OE tOHZ tOE tS tH tCQ DQ0-DQ17 QN-1 DN+2 QN+3 -6- |
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